The present invention relates generally to a logic circuit design apparatus for performing a scan design to a logic circuit whose logic design for normal operation is completed and more particularly, to a logic circuit design apparatus for designing scan circuits for uses peculiar to the logic circuit.
With the advancement of the semiconductor manufacturing process technology in recent years, a logical scale of a logic circuit which can be achieved by one chip has increased. Increasing the logical scale presents greater difficulty in generating a test pattern to test the logic circuit.
A scan design is a technique developed in order to generate the test pattern simply. In the scan design, the memory elements will be connected in such a manner that, on the command of "Test Mode", they will be strung together to form a shift register. That is, by performing the scan design, the logic circuit comes to be able to treated as a combinatorial circuit, so the generation of the test pattern becomes easy.
Moreover, the value maintained in a specific memory element can be read and a specific value can be set in the specific memory element by using the scan circuit. Therefore, the scan circuit can be also used for the maintenance and the like.
The conventional CAD system which has been used for the scan design so far, however, generates the scan circuit for the test pattern generation simplification. Accordingly, the scan circuit is not a suitable one for other uses, such as maintenance. Complex manual work of modifying the logic circuit, on which scan circuits are designed, is necessary to get the scan circuit for a use peculiar to the logic circuit.